VHDL: A Hardware Description Language and its Simulation Semantics

Abstract

VHDL [8,2] is not a formal language like many of the formalisms considered in this book; it is a Hardware Description Language i.e., a language devoted to the description of hardware components at various levels of abstraction. This language has been standardised by the IEEE under the names VHDL’87 and VHDL’93 [5,6]; the VHDL’87 version is considered here. VHDL and another standardised language Verilog [7,9] are used widely by the community of hardware designers. A variety of commercial CAD tools support these languages, providing complete design environments with capabilities for schematic capture, simulation, gate-level or high-level synthesis. VHDL is often used in three different styles of description: the “behavioural” style (clocked or asynchronous concurrent “processes” execute algorithmic specifications and communicate through common “signals”), the “dataflow” style (the architecture of the device is described by means of a set of equations, this style roughly corresponds to the “Register Transfer” level of abstraction), and the “structural” style (the device is described as a set of interconnected components). In this chapter, we consider only the behavioural style.