A Time-Domain Computing Accelerated Image Recognition Processor With Efficient Time Encoding and Non-Linear Logic Operation

Abstract

Time-domain computing (TC) has drawn significant attention recently due to its highly efficient computation for applications such as image processing and neural network computing. This paper presents novel time-domain circuit techniques, including: 1) double-encoding strategy; 2) bit-scalable design that accelerates the performance compared with previous linear coding; and 3) shared time generator (TG) with variation-aware design technique which significantly improves the error tolerance of TC. A feature-extraction and vector-quantization processor accelerated by TC has been developed for real-time image recognition. A 55-nm prototype chip shows 72-fps/core (at 1.33 GHz) operation with up to 42% area and power saving from TC compared to the conventional digital implementation.