Abstract
This paper presents novel time-domain circuit techniques including double encoding strategy, shared time generator (TG) and bit-scalable design which significantly improve the performance of time-domain signal processing (TDSP) and error tolerance. A feature-extraction and vector-quantization processor accelerated by TDSP has been developed for real-time image recognition. A 55nm prototype chip shows 72 fps/core (@1.33 GHz) operation with significant enhancement from time-domain techniques compared with conventional digital implementation.
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