Abstract

A synchronization-free, and all digital design technique for the generation of a spread spectrum clock is presented and simulated in 0.35 μm CMOS technology with a low power consumption of 1.45 mW at 10 MHz. The proposed technique uses a period locking delay-locked loop, multiple phase generator, and a digital controller to modulate the input clock frequency. The peak power of the clock and the supply current are reduced up to 8.5 and 11 dB without any interface circuit for the synchronization between the nonspread spectrum and spread spectrum clock domains.

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