A reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22nm high-k tri-gate LP CMOS

Abstract

As platform integration continues, different modules, including CPU, graphics, I/O interface, wireless transceivers and the power management unit, operate at different frequencies as shown in Fig. 3.8.1. In addition, maximizing battery life requires localized dynamic voltage frequency scaling (DVFS) and sleep mode support leading to independent clock domains for various functional unit blocks (FUBs). Also, clock generation units should be able to go to sleep and wake up rapidly to conserve power. Generating multiple clock signals while minimizing skews at the module interfaces is challenging. Furthermore, some modules require spread spectrum clocking (SSC), with different modulation patterns to avoid EMI, but yet such spreading is forbidden in modules requiring frequency accuracy (e.g. display interfaces). Diverse SSC generation requirements necessitate multiple reference clocks, extra pins, and off-chip components. With analog integer-n PLL-based clock generators, it is difficult to meet all these needs with a common reference clock. One disadvantage is that the frequency resolution in an integer-n PLL is limited by the reference frequency. A lower reference frequency limits the bandwidth and lock time, amplifies jitter from the reference, and increases the loop filter area. Additionally, analog PLLs suffer from unpredictable loop dynamics and clock skews with PVT, mismatch, and transistor leakage, further exacerbated by process scaling. Turning off and waking up an analog PLL requires charging or discharging loop filter capacitors which is inherently slow. This paper presents an all-digital clock generation architecture which (1) provides fractional-n capability in the digital domain; (2) implements SSC within the PLL loop; (3) performs digital clock deskew; and (4) provides dynamic loop bandwidth adjustment to shorten lock time.