Serial ATA testing with analog tester resources

Abstract

Data rate and capacity of a hard disk in computer systems are increasing yearly along with the processor speed. Legacy interface IDE between a computer and hard disk drives is becoming a bottleneck of data transaction speed. Serial ATA is a new high-speed serialized data link introduced for hard disk drives by processor/ hard disk manufacturers. It is gradually replacing the legacy parallel ATA. Serial ATA is one of the serializer/deserializer (SERDES) interfaces, and is purely digital system. However, some unique features such as out-of-band (OOB) signalling, spread spectrum clocking (SSC) are involved so that from the testing point of view there are several challenging items in terms of stimulus generation and measurement techniques. Instead of regular digital testers how mixed signal testers can cope with this serial ATA testing are discussed in this article, introducing several interesting ideas. Generating OOB signalling is not difficult with using an arbitrary waveform generator (AWG), but there is another demand called common mode modulation with a low level of differential signal must be modulated with a low frequency. An attenuator circuit slightly modified to do the task is introduced. SSC is a kind of frequency modulation for data stream. The unit interval of the data bit is slowly wandered intentionally. Generating SSC applied signal is not an easy task for regular digital resources. AWG can take care of SSC applied clock generation easily. SSC applied clock is analyzed its frequency domain spectrum by a sampler. The same data is also processed with orthogonal demodulation method that reveals SSC modulation curves in time domain.