A Sub-μW 3–10MHz Stacked Oscillator with a Duty-Cycle Calibrated Level Shifter

Abstract

The ring oscillator is the topology of choice in many modern applications given its simplicity, small area footprint, low-power and ability of being implemented with digital inverters. The oscillation frequency is dictated by the number of stages in the chain and the average delay of the inverters. In deep submicron processes, the very short propagation delay of logic gates makes the ring oscillator a very energy-efficient solution for high frequencies of operation, whereas for low frequencies the efficiency generally drops because larger capacitances must be driven to slow down the transitions. In this paper we propose a topology of oscillator that employs four injection-locked stacked ring oscillators, reusing current while the available supply potential is divided among these stages, naturally reducing the oscillation frequency while maintaining energy efficiency. The output signal is recovered to the supply rails through a level shifter circuit with feedback, allowing to adjust its threshold to deal with PVT variations. Simulation results show that the circuit operates from 3–10 MHz, while consuming 0.7 μW at 10 MHz, with a phase noise of −88.8 dBc/Hz at 100 kHz offset, leading to a FoM of −160 dB.