An Ultra-Low-Voltage Energy-Efficient Dynamic Fully-Regenerative Latch-Based Level-Shifter Circuit with Tunnel-FET & FinFET Devices

Abstract

Circuits based on tunneling FET (TFET) devices are fueling the beyond CMOS logic design, meeting the ultra-low-power demands for Internet-of-Things (IoT) applications. This paper presents a highly energy-efficient hybrid TFET/FinFET level shifter (LS) circuit, providing a robust signal up-conversion from deep subthreshold voltage. A pulse-triggered dynamic fully-regenerative latch and two modified dynamic current generators are incorporated to overcome the timing variation of input differential signals and current contention in the cross-coupled circuit. The simulation results show that the hybrid TFET/FinFET LS circuit has achieved a low propagation delay, dynamic power consumption, and power-delay-product (PDP) of ≤378 ps, ≤39.6 μW, and ≤13,950 ns-nW, respectively while converting the input signal from the ultra-low-voltage of sub-50mV to the nominal supply voltage of FinFET (0.8-1.2V). The proposed architecture has achieved up to 2.71-to-15.99x improvement in PDP compared to the reported state-of-the-art LS architectures.