Abstract
A millimeter-wave power amplifier (PA) implemented in a commercial 45nm CMOS SOI technology is presented. The PA design is based on stacking of two dynamically-biased Cascode transistor cells where drain-source voltages of individual transistors are added constructively to increase the output power. The PA output impedance is the sum of the output impedances of the two Cascode cells and is optimized to match to a 50 Ω load. At the operating frequency of 50 GHz and under a power supply of 4 V, the PA provides a saturated output power P SAT of 19 dBm (~80 mW), a -1dB output compression point (P 1dB ) of 16.3 dBm and a peak power-added efficiency (PAE) and drain efficiency (DE) of 28% and 40%, respectively.
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