Abstract
A reconfigurable CMOS inverter-based stacked power amplifier (PA) is proposed to extend impedance coverage, while maintaining an output power exceeding the specific power level under the worst antenna impedance mismatch conditions. The adopted process technology supports multi-threshold metal-oxide-semiconductor field-effect transistor (MOSFET) devices, and therefore, the proposed PA employs high threshold voltage (Vth) MOSFETs to increase the output voltage swing, and the output power under a given load condition. The unit cell of the last PA stage relies on a cascode inverter that is implemented by adding cascode transistors to the traditional inverter amplifier. By stacking two identical cascode inverters, and enabling one or both of them through digital switch control, the proposed PA can control the maximum output voltage swing and change the optimum load Ropt, resulting in maximum output power with peak power added efficiency (PAE). The cascode transistors mitigate breakdown issues when the upper cascode inverter stage is driven by a supply voltage of 2 × VDD, and decrease the output impedance of the PA by changing its operation mode from the saturation region to the linear region. This variable output impedance characteristic is useful in extending the impedance coverage of the proposed PA. The reconfigurable PA supports three operation modes: cascode inverter configuration (CIC), double-stacked cascode inverter configuration (DSCIC) and double-stacked inverter configuration (DSIC). These show Ropt of around 100, 50 and 25 Ω, respectively. In the simulation results, the proposed PA operating under the three configurations showed a saturated output power (Psat) of +6.1 dBm and a peak PAE of 41.1% under a 100 Ω load impedance condition, a Psat of +4.5 dBm and a peak PAE of 44.3% under a 50 Ω load impedance condition, and a Psat of +5.2 dBm and a peak PAE of 37.1% under a 25 Ω load impedance condition, respectively. Compared to conventional inverter-based PAs, the proposed design significantly extends impedance coverage, while maintaining an output power exceeding the specific power level, without sacrificing power efficiency using only hardware reconfiguration.
Highlights
As wireless electronic devices continue to be miniaturized, and further support multi-functionality, antenna size reduction is required because most mobile platforms have a limited space for all of the necessary antennas
Because most power amplifier (PA) are designed to drive a standard 50 Ω impedance load using a dedicated output matching network, antenna impedance mismatch significantly affects peak output power and power-added efficiency (PAE) performance. It was reported by Keerti et al that the output power of a PA decreases as much as 5 dB for a load mismatch with a voltage standing-wave ratio (VSWR) of 10:1 [1]
PA operated in the cascode inverter configuration (CIC), double-stacked cascode inverter configuration (DSCIC) and double-stacked inverter configuration (DSIC)
Summary
As wireless electronic devices continue to be miniaturized, and further support multi-functionality, antenna size reduction is required because most mobile platforms have a limited space for all of the necessary antennas. Regarding integrated tunable capacitors in CMOS, the most common topology of the digitally controlled switched capacitor array inevitably faces a fundamental trade-off between the Q-factor and the tuning range [5], and its performance degrades as the operating frequency increases Some emerging technologies, such as micro-electro-mechanical systems (MEMS) and barium strontium titanate (BST), have been proposed for use in the implementation of low-loss, wide-tuning-range tunable capacitors [6,7]. These technologies require a high tuning/switching voltage (>30 V), which is unsuitable in battery-driven mobile handsets. Without a TMN, impedance coverage was significantly extended compared to the conventional inverter-based PAs, maintaining an output power exceeding the specific power level without sacrificing power efficiency
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