Abstract
This work presents a high efficiency, highest reported output power GaN-based power amplifier targeting the V-band frequency range from 65 to 71 GHz. Implemented in HRL’s 40 nm GaN T3 MMIC process and simulated in AWR, the presented power amplifier achieves a simulated peak power added efficiency (PAE) of 34.9% at 66 GHz. The PA is composed of three stages, and the output stage uses a 4:1 Wilkinson power combiner. The PA’s maximum linear power gain is 13.3 dB at 68 GHz for an input power of 13 dBm. The maximum output power at 1dB compression point is 35.1 dBm at 68 GHz, associated with an input power of 23 dBm. The chip size is 2.7×4.9mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , thus demonstrating a high power density of 245 mW/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in simulation.
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