A Spike-Latency Transceiver With Tunable Pulse Control for Low-Energy Wireless 3-D Integration

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Wireless 3-D integration using inductive coupling links (ICLs) has recently gained attention as a low-cost alternative to through-silicon vias (TSVs) for interconnecting stacked silicon tiers. However, 3-D integration using ICLs is often criticized for its inferior energy efficiency compared with conventional approaches. To address this challenge, in this article, we present a low-energy ICL transceiver that combines a spike-latency encoding scheme (to reduce the number of energy-expensive analog transmit pulses by encoding data in the time domain) and a tunable current driver (to minimize the transmit energy depending on the given integration scenario). The proposed transceiver is modeled mathematically, simulated in 0.35- $\mu \text{m}$ , 65-nm, and 28-nm CMOS technologies and experimentally validated in a two-tier 3-D stacked silicon test chip. Silicon evaluation of the proposed modulation approach demonstrates an energy of 7.4 pJ/bit, representing a reduction >13% when compared with previously reported schemes (or 7.4% when also considering the additional energy overheads of peripheral clock timing control circuits). The simulated results show even greater energy savings (up to 28%) at more advanced technology nodes. Combined with the adaptive current driver, this results in a $7.7\times $ improvement in energy per bit compared with the state-of-the-art implementations across the same communication distance, marking an important progression toward cost and energy-efficient 3-D integration.