A simple, approximate representation of the electrical behaviour of metal-silicon contacts

Abstract

Normally a metal-semiconductor contact is viewed as consisting of three distinct materials [1]: metal, a "native oxide" layer which is, in fact, of unknown composition, and semiconductor. The contact is held to be electrically characterized by its contact resistivity or specific contact resistance, which is the resistance per unit area (actually the resistance x area product). The contact interface is regarded then as a two-dimensional network of infinitesimal resistances connecting the metal to the bulk, which is itself a three-dimensional network of infinitesimal resistances. In previous work on electrical contacts to semiconductors, much effort has been expended on developing suitable test structures for measuring contact resistivity [1-4], and in refining the analysis of existing test structures [5, 6]. However, little attention has been paid to the fact that there does not appear to be a homogeneous interface layer. The evidence for this is the rather large scatter in measured resistances usually obtained in experiments [4, 7-10]. In an earlier paper [10] we showed that the source of the scatter in resistance was more likely to be variation in the contact resistivity than fluctuation in the contact window dimensions [4, 7]. Upon further reflection and examination of our experimental results, we find that the concept of contact resistivity, itself, requires modification. This, at least, appears to be the case for aluminium contacts to p-type silicon, but judging from the scatter in resistance observed for other metals and materials [9], may be true generally. The fall in contact resistance observed during the initial stage of annealing [8] gives evidence for penetration of an impurity film or native oxide layer. It is also known that aluminium dissolves silicon at the elevated temperature of annealing. The aluminium-doped silicon later deposits on the substrate during cooling, as may be inferred from the work of Naguib and Hobbs [8]. It is suggested here that the deposit occurs in patches in the contact window. Evidence for this has appeared in quite another context in the work of Black [11]. To model the electrical behaviour of the contact corresponding to this metallurgical condition, we must consider the equivalent electrical circuits that arise. We consider first the case of lightly doped p-type silicon. Away from precipitates there must exist a Schottky barrier as well as a bulk resistance, whereas in the vicinity of precipitates the conduction is essentially that occurring in the pure bulk material. For heavily doped silicon and for regions free of