A Segmented Digital Pulse Width Modulator with Self-Calibration for Low-Power SMPS

Abstract

The next-generation, digitally controlled DC-DC converters require a high frequency, high resolution, low power and area efficient digital pulse width modulator (DPWM). This paper introduces a self-calibrated segmented DPWM that uses a delay-locked loop to calibrate adjacent delay segments. An 8-bit prototype designed in a 0.13-μm CMOS process operates at a switching frequency of 11.6 MH z , draws 190μA from a 1.2 V supply and occupies only 0.0075 mm2.