Abstract
3D Physical simulation has been used to analyse the impact of substrate parasitic elements on HBT electrical characteristics. A geometry scalable SPICE model is proposed and the resulting electrical simulation results are compared with physical simulation results. All lumped elements can be calculated directly from layout and technological data. The model is implemented in the scalable HBT compact model HICUM Level 0. A comparison with respect to measurements from a 0.25 μm BiCMOS technology with several HBT emitter areas shows an improvement of the simulation results.
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