A Reconfigurable Approximate Computing Architecture With Dual-VDD for Low-Power Binarized Weight Network Deployment

Abstract

Approximate computing (AC) is an innovative paradigm for error-resilient signal processing applications. Addition is often a fundamental function for many of these applications. Particularly, binarized weight network (BWN) eliminates the multiplication by quantizing the weight to 1 bit, and the convolution can be achieved by simple accumulation. To further improve the energy efficiency of BWN, an approximate computing architecture based on the reconfigurable approximate adder with dual-VDD is proposed. The precision of the proposed approximate addition structure can be configured by setting approximate bit-width (ABW), and different voltage supplies can be configured for the approximate adder to reduce power consumption. A keywords-spotting (KWS) processor based on an optimized BWN is then used as a case study of the proposed approximate computing architecture. Implemented and evaluated under 22nm technology, the power consumption of the proposed BWN accelerator can be reduced by 54.3%, while the accuracy loss is only 0.4%.