Abstract
In this paper, a reconfigurable architecture of CLEFIA block cipher which supports multi-configuration is proposed. Moreover, different generalized Feistel networks are integrated into a novel folding structure, which not only increases the circuit flexibility but also reduces the hardware overhead. Besides, the processes of generating intermediate key and encryption share the same circuit by time-division multiplexing technology to reduce the hardware resource consumption further. The proposed CLEFIA design is implemented in Artix-7 XC7A35 T FPGA board. Measurement results show that it can realize all the three CLEFIA configurations of key size, which are 128/192/256-bit, with a few resources of 1725 look-up-tables and 663 registers. At a clock frequency of 147 MHz, it also reaches high throughputs of 990 Mbps, 818 Mbps, and 696 Mbps in the three configurations respectively.
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