Abstract
An asynchronous successive approximation register analog-to-digital converter (ADC) for wideband multi-standard systems is presented. The ADC can be configured as an 80-MS/s 10-b, 40-MS/s 11-b, or 20-MS/s 12-b converter. Time-interleaved technique is applied to expand sampling bandwidth exponentially while resolution scales down. The channel mismatches are cancelled by the digital calibration technique. The bulk-biasing technique is used in the sampling switch to reduce the influence of the charge injection caused by the top-plate sampling. In addition, the configurable asynchronous processing is employed to extend the flexibility of speed and resolution tradeoff. Moreover, the two-step digital-to-analog converter (DAC) switching method is proposed to reduce the switching energy of the DAC. Prototyped in 180-nm CMOS process, the ADC achieves the 56.7-/61.2-/64.6-dB signal-to-noise and distortion ratio (SNDR) and 72.3-/74.8-/75.5-dB spurious-free dynamic range (SFDR) at 80-/40-/20-MHz sampling frequency with the power consumption of 2.61/2.05/1.77 mW.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: IEEE Transactions on Circuits and Systems I: Regular Papers
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
