Abstract
This paper presents an energy-efficient low power 10-b 8-MS/s asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter. An inverted common-mode charge recovery technique is proposed to reduce the switching energy and to improve the linearity of the digital-to-analog converter (DAC). The proposed switching technique consumes only 149 CVREF2 switching energy for the 10-bit case. A rail-to-rail dynamic latch comparator is implemented with adaptive power control for better power efficiency. Additionally, to optimize the power consumption and performance of the logic part, a modified asynchronous type SAR control logic with digitally controllable delay cells is adopted. An on-chip reference voltage generator is also designed with an ADC core for practical use. The structure is realized using 55-nm complementary metal–oxide–semiconductor (CMOS) process technology. The proposed architecture achieves an effective number of bits (ENOB) of 9.56 bits and a signal-to-noise and distortion ratio (SNDR) level of 59.3 dB with a sampling rate of 8 MS/s at measurement level. The whole architecture consumes only 572 µW power when a power supply of 1 V is applied.
Highlights
Successive approximation register (SAR) analog-to-digital converters (ADCs) have emerged as the best option for meeting the requirement of low power consumption, high speed, and medium resolution among different ADC architectures
Based on the asynchronous successive approximation register (SAR) logic, when the conversion cycle is completed it generates an end of conversion (EOC) signal
This paper presents a low power 10-bit asynchronous SAR ADC with an on-chip reference voltage generator operating at a sampling rate of 8 MS/s
Summary
Successive approximation register (SAR) analog-to-digital converters (ADCs) have emerged as the best option for meeting the requirement of low power consumption, high speed, and medium resolution among different ADC architectures. For low power and medium conversion speed, the SAR type ADC is among the best available choices as in its operation, full conversion is divided into several comparison phases by using only one comparator [10]. In a conventional synchronous SAR ADC, the sampling process and all conversion steps are done according to an external clock. It needs at least (N + 1) number of clock cycles to complete its operation and produce the output for an N bit ADC
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