A quantitative performance analysis of FinFET based multiplier circuits

Abstract

In this paper, we investigate and compare the performance of four different FinFET based multiplier topologies in terms of their leakage power, dynamic power, delay and power delay product at the transistor level. The multiplier topologies analyzed are Ripple Carry Array multiplier, Carry Save Array multiplier, Wallace Tree multiplier and Baugh-Wooley multiplier. The circuit simulations were performed in HSPICE using 20nm, and 14nm low-power FinFET models. 16×16 and 32×32 bit multiplier architectures were implemented for each topology. The results show that the Baugh-Wooley multiplier has the best power performance among all the multipliers investigated. The Wallace tree multiplier is the fastest among the all the multipliers for the 16×16 multiplier architecture. As the number of input bits increased, the Baugh-Wooley multiplier exhibited better power delay product. The results of this research is expected to provide a starting point for the design and analysis of more complex FinFET based circuits at transistor level.