A Programmable Frequency Divider for Multi-Standard Wireless Receivers

Abstract

A programmable frequency divider based on divider-by-2/3 structure in fractional-N frequency synthesizer is presented, including a high speed divider-by-2 providing orthogonal signals for mixer. This paper firstly introduces two structures of programmable frequency divider, and analyzes the rationality of the circuit structure. Then it presents a method to determine the parameters of CMOS transistors in SCL structure. Finally, each component of the circuit is analyzed. The simulation results show that the programmable divider can work at 1 ~ 8 GHz and generates programmable division ratio from 32 to 127. This programmable frequency divider can be used in mobile communications, satellite navigation, short distance communication and other systems.