A Preliminary Study of Oscillators, Phase and Frequency Detector, and Charge Pump for Phase-Locked Loop (PLL) Applications

Abstract

The great advancement in CMOS technology, high speed and frequency, low jitter, low noise and phase noise, and less expensive phase-locked loop are very important in transceiver fields. This work aims at reviewing the performance of oscillators, phase and frequency detector (PFD), and charge pump (CP) for type-I PLL. In this work, the oscillators are reviewed as voltage-controlled oscillators (VCOs) and coherent-based phase-locked synchronous oscillator (CPSO). The phase and frequency detector is evolved as XOR gate PFD, double edge-triggered PFD, and digital pulse amplifier. The condition for stable operation and low-phase noise is established. The different types of oscillators and PFDs are reviewed. A detailed analysis of various methods to design oscillator, phase and frequency detector is provided. The best method to design phase and frequency detector is digital pulse amplifier. It minimizes the dead zone and phase error that can be easily recognized by flip-flop which is type D, and this amplifier has AND gates and is connected in series to raise the pulse width. The best method to design an efficient oscillator is the coherent phase-locked synchronous oscillator from various oscillators under study. It provides a method for improved frequency and lock-in range, capture range over the other oscillators. It retains the normal oscillator characteristics with less phase shifts across the frequency tuning and locking range.