A 8 Gb/s Si bipolar phase and frequency detector IC for clock extraction

Abstract

A clock recovery (CR) approach based on a phase and frequency detector (PFD) has been implemented in a phase-and frequency-locked loop (PFLL). CR controlled by a PFD has been demonstrated up to 4 Gb/s. The Si bipolar PFD presented here operates up to 8 Gb/s, demonstrating its application in a PFLL. A block diagram is presented which shows that the input data stream samples the VCO signal and the delayed VCO signal (delay about 90 degrees ) in two sample-and-hold cells (S/H) that serve as phase detector (PD) and quadrature phase detector (QPD), respectively. >