Abstract
In high-speed digital systems and high-resolution display devices, the jitter effect of phase-locked loops (PLL) limits the system performance. Power supply noise coupling is one of the major causes of PLL jitter problems, especially with mixed-signal systems. The paper presents a targeted 5.0V 500 MHz PLL which is implemented by a 0.6 um 1P3M digital CMOS technology. The features of the proposed design include a load-optimized 3-stage VCO, a frequency limiter RC circuit, and a ratioed VCO controlling current mirror. The jitter, thus, is reduced to 72.693 ps at 600 MHz at the presence of supply noise, while the sensitivity is limited to 286.6 ps/V. This high-noise immunity design allows that the PLL can be integrated with digital circuits.
Highlights
phase-locked loops (PLL) are often used in the I/O interfaces of digitalICs in order to hide clock distribution delays and improve the overall system timing [5] or high frequency clock generators [2, 3, 7]
We present a PLL design including a load-optimized 3-stage VCO, a frequency limiter RC circuit, and a ratioed VCO controlling current mirror
The entire design is implemented by TSMC (Taiwan Semiconductor Manufacturing Company) 0.6 um 1P3M CMOS technology and verified by HSPICE
Summary
5V 500 MHz Digital Phase-locked Loop* CHUA-CHIN WANG YU-TSUN CHIEN and YING-PEI CHEN. In high-speed digital systems and high-resolution display devices, the jitter effect of phase-locked loops (PLL) limits the system performance. Power supply noise coupling is one of the major causes of PLL jitter problems, especially with mixed-signal systems. The features of the proposed design include a loadoptimized 3-stage VCO, a frequency limiter RC circuit, and a ratioed VCO controlling current mirror. The jitter, is reduced to 72.693 ps at 600 MHz at the presence of supply noise, while the sensitivity is limited to 286.6 ps/V. This high-noise immunity design allows that the PLL can be integrated with digital circuits
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