Abstract
With more cores integrated into a single chip and the fast growth of main memory capacity, the DRAM memory design faces ever increasing challenges. Previous studies have shown that DRAM can consume up to 40% of the system power, which makes DRAM a major factor constraining the whole system’s growth in performance. Moreover, memory accesses from different applications are usually interleaved and interfere with each other, which further exacerbates the situation in memory system management. Therefore, reducing memory power consumption has become an urgent problem to be solved in both academia and industry. In this paper, we first proposed a novel strategy called Dynamic Bank Partitioning (DBP), which allocates banks to different applications based on their memory access characteristics. DBP not only effectively eliminates the interference among applications, but also fully takes advantage of bank level parallelism. Secondly, to further reduce power consumption, we propose an adaptive method to dynamically select an optimal page policy for each bank according to the characteristics of memory accesses that each bank receives. Our experimental results show that our strategy not only improves the system performance but also reduces the memory power consumption at the same time. Our proposed scheme can reduce memory power consumption up to 21.2% (10% on average across all workloads) and improve the performance to some extent. In the case that workloads are built with mixed applications, our scheme reduces the power consumption by 14% on average and improves the performance up to 12.5% (3% on average).
Highlights
With the widespread use of chip multiprocessors and rapid growth of the I/O speed, multiple applications running in parallel have increasing demand in the accessing speed and the capacity of the memory system
Multiple independent memory access streams to di®erent banks run in parallel, called Bank Level Parallelism (BLP), which can hide the latency by pipelining memory accesses
By integrating Dynamic Bank Partitioning (DBP) with adaptive page policy, our work aims at reducing the memory power consumption and improving the system performance simultaneously. 3.2
Summary
With the widespread use of chip multiprocessors and rapid growth of the I/O speed, multiple applications running in parallel have increasing demand in the accessing speed and the capacity of the memory system. To improve the system performance, manufactures tend to increase chip integration density and memory bandwidth Such practice leads to even higher memory power consumption. With the increasing number of cores on chip, memory accesses from di®erent cores interfere with each other Such interference ruins the original characteristics of an application's memory accesses and leads to low spatial locality, greatly reducing system performance and increasing power consumption.[2] Experiments in Ref. 3 show that when the LBM benchmark was running alone, the hit rate could reach up to 98% and its memory accesses exhibited large amount of special locality. In multi-core systems, dynamic bank partitioning keeps the original characteristics of each core, which provides the opportunity for exploiting the spatial locality to reduce memory power consumption.
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