Abstract
With the rapid development of integrated circuits [1], low power consumption has become a constant pursuiting goal of the designer in chip design. As the memory almost takes up the area of the chip, reducing memory power consumption will significantly reduce the overall power consumption of the chip; according to ISSCC’s 2014 report about technology trends discussions, there two points of the super-low power SRAM design: 1) design a more effective static and dynamic power control circuit for each key module of SRAM; 2) ensure that in the case of the very low VDD min, SRAM can operating reliably and stably. This paper makes full use reliable of 8T cell, and the single-port sense amplifier has solved problems in the traditional 8T cell structure, making the new structure of the memory at a greater depth still maintain good performance and lower power consumption. Compared with the designed SRAM the SRAM generated by commercial compiler, as the performance loss at SS corner does not exceed 10%, the whole power consumption could be reduced by 54.2%, which can achieve a very good effect of low-power design.
Highlights
The most effective way to reduce power is the use of very low power supply voltage, for the relationship between the power consumption and the supply voltage is: the power consumption is proportional to the square of the supply voltage; for static power consumption, the low-voltage design techniques is the most direct and effective way, because leakage power will be low enough when SRAM power supply voltage is low enough
The design of the SRAM structure proposed in this paper is using 8-T cell, because of its better stability than6-T, 8T is a big trend of future development
Power consumption was lower than memory compiler SRAM
Summary
The most effective way to reduce power is the use of very low power supply voltage, for the relationship between the power consumption and the supply voltage is: the power consumption is proportional to the square of the supply voltage; for static power consumption, the low-voltage design techniques is the most direct and effective way, because leakage power will be low enough when SRAM power supply voltage is low enough. In this thesis, based on a 65 nm process single-port sense amplifier, designed an 8T_SRAM circuit, and compared this SRAM with the generated SRAM by memory compiler in performance, on the premise of speed quite, the former has much more advantage in power and stability. (2015) Design and Implement of Low Power Consumption SRAM Based on Single Port Sense Amplifier in 65 nm.
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