A novel VLSI architecture for full-search variable block-size motion estimation

Abstract

Variable block-size motion estimation (VBSME) has become an important technique in H.264/AVC to improve video quality. In this paper, we propose a scalable VLSI architecture for VBSME in H.264/AVC based on a full-search motion estimation algorithm. A new scan order is introduced to re-use the sum of absolute differences (SAD) values of smaller sub-blocks on an as-early-as-possible basis, thus the complexity of the required hardware resources, such as registers, multiplexers, and controls is reduced. It also spreads the timing for the final SAD outputs so that the number of output buses is reduced. The architecture is flexible and scalable with regard to the size of the searching windows and PE arrays. Compared to the conventional approaches, the architecture shows higher throughput rate with less hardware. After logic synthesis using DongbuAnam 0.18 mum standard cell library, the number of gates is 39K (16 PEs) in two-input equivalent NAND gates and the maximum operating clock frequency is 416 MHz (256 fps@CIF).