Abstract
A novel techniques for a gated silicon field emission cathode is proposed in order to decrease the spacing between tip and gate electrode of the device, leading to low voltage operation. This technique is based on the penetration of the sputtered Ti/sub 0.1/W/sub 0.9/ for the gate electrode into the shadowed area surrounding the tip with good step coverage, and is completely compatible to the conventional 1.2 /spl mu/m CMOS standard processes. The experimental results indicate that the gate hole diameter is greatly reduced to sub-half micron (/spl sim/0.4 /spl mu/m) from the initial mask size (/spl sim/1.2 /spl mu/m), and I-V characteristics of the cathodes show low turn-on voltages (/spl sim/25 V) in ultrahigh vacuum (<3.0/spl times/10/sup -7/ Torr) and the good linearity of Fowler-Nordheim plots.
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