Abstract
A novel structure of silicon field emission cathode with the narrow spacing between tip and gate electrode is proposed, leading to a low voltage operation. It utilizes the filling characteristics of the sputtered Ti/sub 0.1/W/sub 0.9/ beneath the disc-shaped tip-mask oxide with good step-coverage. TEOS (tetraethylorthosilicate) oxide is used for gate dielectric and it shows good leakage characteristics. Without advanced lithography technology, the gate hole diameter is greatly reduced to sub-half micron of /spl sim/0.4 /spl mu/m from the initial tip-mask size of /spl sim/1.2 /spl mu/m. Uniform and stable silicon field emission cathode is obtained using well-established VLSI process technologies. I-V characteristics of the cathodes show low turn-on voltages of /spl sim/30 V.
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