A novel process variation tolerant wide fan-in dynamic OR gate with reduced contention

Abstract

Register file structures in modern microprocessors usually employ wide fan-in dynamic CMOS OR gates. Weak keepers have been traditionally used to resolve the low noise margin problem of dynamic CMOS design. Scaling trends and process variation issues in CMOS design have reduced the effectiveness of this weak PMOS keeper. On the other hand large sized PMOS keeper used in wide fan-in dynamic OR gate results in contention between the pull down network (PDN) and the keeper. As a consequence of contention there is an unnecessary increase in power dissipation and loss in performance. In this paper a process variation tolerant wide fan-in dynamic OR gate with a new keeper design is proposed which is capable of reducing the contention between the keeper and PDN and hence capable of reducing the power dissipation and delay. Simulation results at 50nm shows that the power dissipation and delay have been reduced by 40% and 35% respectively as compared to the wide fan-in dynamic OR gate with conventional keeper under different levels of process variation.