A NBTI tolerant technique for FinFET based wide fan-in dynamic logic

Abstract

With the aggressive scaling trend in the VLSI technology the NBTI effect has emerged as a major reliability concern for both CMOS as well as FinFET based circuits. NBTI causes an incremental deviation in the threshold voltage of PMOS and hence causes variation in performance and timing of digital circuits. This timing mismatch is a serious issue for synchronous clock based circuits such as dynamic logic gates. Further NBTI may increase the delay of circuits which are lying in the critical path of a system and may lead to failure of system. This NBTI caused delay can be a serious issue for wide fan-in dynamic OR gate lying in the critical path of a high speed microprocessor. In this work the impact of NBTI on the FinFET based wide fan-in dynamic OR gate has been analysed. A novel sensor based NBTI tolerant FinFET dynamic logic OR gate has also been proposed here to overcome any degradation in performance due to NBTI. Proposed design makes use of double gate FinFET back gate biasing technique to maintain a constant threshold voltage of the transistors under NBTI degradation. Proposed design is capable of maintaining a stable performance of dynamic OR gate with only 1.8 % variation in delay for a lifetime of 10 years.