A Novel OPC Technique for 2D Critical Dimension Optimization of Sub-micron Patterns using an Experimental Methodology

Abstract

As the development of the ULSI technique with respect to the decrease in the feature sizes, critical dimension has become a vital parameter for the IC manufacturing. For sub-micron technologies, there has always been a significant mismatch between the layout and post lithography patterns. Since most of the conventional optimization techniques are model based, it is quite hard to obtain a good accuracy for a real-world solution. Moreover, these methods can not easily be integrated to any fabrication environment. This paper presents a layout correction technique which uses a look-up table of measured patterns with 0.3um and 0.4um critical dimensions. An interpolation method that takes the design grids into account has been used to obtain the optimum layout for sub-micron ULSI circuits. This paper not only focuses on an experimental and accurate critical dimension optimization, but also draws attention how to implement this methodology for any fabrication environment.