Abstract
In this paper, a novel, planar, multi-cell lateral insulated gate bipolar transistor in the double epitaxial layer dielectric isolation technology is proposed for the first time. This multi-cell lateral insulated gate bipolar transistor exhibits a unique quasi-vertical mode of operation to achieve a localised conductivity modulation in the sandwich region between the adjacent cathode cells. Analysis shows that a significantly performance is achievable without affecting its switching and blocking capability. Most importantly, this approach does not require additional fabrication steps to an existing HV-CMOS process and therefore, is highly cost and area efficient.
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