Abstract

This paper presents a new CMOS four-quadrant low voltage and low power analog multiplier circuit in voltage mode. In the proposed analog multiplier, transistors are biased in weak inversion by driving them at bulk terminals. The proposed design has fully differential ended output. Input signal ranges are ±40mV and all transistors have the equal sizes. Simulation results have been presented by HSPICE simulator in 0.18μm standard CMOS technology to confirm the operation of the circuit. The results show that the proposed analog multiplier has several advantages in comparison with other analog multipliers.

Full Text
Paper version not known

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.