Design of Low-Voltage and Low-Power DTMOS Based Analog Multiplier Utilizing Current Squarer

Abstract

ABSTRACT In this paper, a low-voltage and low-power current mode analog multiplier design is presented. The multiplier is based on dynamic threshold MOS (DTMOS) structure. The proposed topology consists of four current squarer circuits and one subtractor structure. Each squarer cell has two MOS transistors and the subtractor consists four MOS transistors. Therefore, the multiplier employs 12 MOS transistors excluding resistors and biasing current sources. The introduced circuit consumes low power and requires low voltage power supplies thanks to DTMOS structure. The current mode analog multiplier architecture has a power consumption of 99.76nW and involves a single supply voltage of 0.3 V owing to including DTMOS transistor. The analysis results agree well with the expected results. The behaviour of the suggested multiplier has been verified through the analysis results with the help of LTspice simulation software and 0.13 µm IBM CMOS technology parameters have been used for simulation.