A 1-V fully differential sample-and-hold circuit using hybrid cascode compensated DTMOS-based folded OTA

Abstract

This paper presents the design and preliminary results of a sample-and-hold circuit based on a novel implementation of a dynamic threshold MOS (DTMOS) hybrid compensated folded OTA. The heart of this circuit is a new low-voltage fully-differential hybrid cascode compensated DTMOS folded OTA. The use of DTMOS reduces the input/output common mode requirement on the OTA input while hybrid cascode compensation yields to a higher amplification bandwidth compared to the standard Miller and compensation techniques. To overcome input sampling switch limitations imposed by the low supply voltage we make use of a low-voltage low stress and reliable clock signal doubler. Preliminary post-layout simulation results in a 0.18 mum digital CMOS process show that a resolution greater than 8 bits can be obtained with a 1.0 V supply voltage using a 2 MHz clock signal. Further investigations on the performance limit of the proposed method as well as reliability concerns will be performed on the final experimental test chip.