Abstract
In Analog application, multipliers plays a vital role. They are used in many fields like artificial neural networks, image processing, modulators etc. In this paper, a low power and low voltage CMOS analog multiplier is presented with performance analysis and design implementation by using Exponential Approximation circuit. In this design, MOSFETS are operating in weak inversion region in order to achieve low power dissipation. Multiplier consists of four such Exponential approximation circuits which is operating at a supply of 0.5V. Results and simulations are carried out by using 180nm technology in Tanner tool. Total power consumption is 598nW. T-Spice simulation and result shows that the proposed structure has very low power consumption which makes it attractive for using in various analog circuits.
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