Abstract

The design procedure for a low power continuous-time linearised Gm-C filter based on the operation of the FGMOS transistor in the weak inversion region has been presented in this chapter. The technique is specially suitable for very low frequency applications in which dynamic range and power consumption are the most important issues. This chapter describes a linearised Gm-C topology in which the linearisation is achieved by means of two 'floating gate' blocks: a nonlinear transconductor with three output currents and a square-root block based on FGMOS transistors biased in the weak inversion region that processes the three currents provided by the first block, thus giving rise to a fully linear topology.

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