A Novel LDPC Construction Scheme for NAND Flash Memory

Abstract

The storage capacity of NAND Flash memory has increased by scaling down to smaller cell size and using multi-level storage technology, but data reliability is degraded by severer retention errors. As adopting a very powerful error-correcting code gradually becomes a strategic demand for the endurance of nowadays NAND Flash memory, Low Density Parity Check (LDPC) codes are recently proposed due to their outstanding error correcting capability. Herein, a novel construction scheme of LDPC for NAND Flash memory is proposed. By using the proposed scheme, a high code-rate, high performance of Bit Error Rate (BER), low error floor Quasi Cyclic Low Density Parity Check (QC-LDPC) code is constructed to meet the needs of NAND Flash memory. In the proposed LDPC construction scheme, iterative cycle elimination technique is introduced to ensure that the checksum matrix is cycle-4 free and has minimal cycle-6, which is beneficial to achive high performance of BER and low error floor for high code-rate LDPC. A diagonal coding structure is used in the QC-LDPC code to achieve linear-time coding and meet the high throughput requirements of NAND Flash memory. Simulation results show that NAND Flash memory can be used more 1800 times for Program/Erase (P/E) cycle by using the proposed QC-LDPC codes compared with Euclidean-Geometry LDPC codes. The error floor of the constructed QC-LDPC codes is below 1$0^{-12}$.