A Novel High-Speed 54Ã—54 bit Multiplier

Keivan Navi,Pouya Asadi

doi:10.3844/ajassp.2007.666.672

Abstract

A new 54×54-bit multiplier using high-speed carry-lookahead adder has been fabricated by CMOS technology. This paper presents a self-timed carry-lookahead adder in which the logic complexity was a linear function of n, the number of inputs, and the average computation time was proportional to the logarithm of the logarithm of n. To the best of our knowledge, our adder has the best area-time efficiency. A novel 4-2 compressor, featuring pass-transistor multiplexers, has been developed. The proposed circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages was minimized due to the high logic functionality of pass- transistor multiplexers. The total number of transistors of the proposed multiplier core was 42579 and The multiplication time was 3.4 ns at a 1.3 V power supply.

Highlights

MATERIALS AND METHODSMultiplication is one of the basic arithmetic operations
Having high speed multipliers is critical for the performance of processors
Of total cell area and the power consumption is even less than 1% of total power consumption in a 54×54-bit multiplier

Summary

Introduction

Multiplication is one of the basic arithmetic operations. 8.72% of all instructions in a typical scientific program are multiplies[1]. In typical processes multiplication takes between 2 and 8 cycles[2]. Having high speed multipliers is critical for the performance of processors. Processor designers have recognized this, and have devoted considerable silicon area for the design of multipliers[3]. Recent advances in integrated circuit fabrication technology have resulted in both smaller feature sizes and increased die areas[4]. Together, these factors have provided the processor designer the ability to fully implement highspeed floating point multipliers in silicon

Methods

Findings

Conclusion