A 4.4 ns CMOS 54×54-b multiplier using pass-transistor multiplexer

N Ohkubo,M Suzuki,K Sasaki,T Yamanaka,T Shinbo,A Shimizu,Y Nakagome

doi:10.1109/4.364439

A 4.4 ns CMOS 54×54-b multiplier using pass-transistor multiplexer

N Ohkubo, M Suzuki + Show 5 more

https://doi.org/10.1109/4.364439

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Journal: IEEE Journal of Solid-state Circuits	Publication Date: Mar 1, 1995
Citations: 171

Affiliation: Hitachi (Japan)

#Carry Lookahead Adder #Conventional CMOS Circuits + Show 8 more

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Abstract

A 54/spl times/54-b multiplier using pass-transistor multiplexers has been fabricated by 0.25 /spl mu/m CMOS technology. To enhance the speed performance, a new 4-2 compressor and a carry lookahead adder (CLA), both featuring pass-transistor multiplexers, have been developed. The new circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages is minimized due to the high logic functionality of pass-transistor multiplexers. The active size of the 54/spl times/54-b multiplier is 3.77/spl times/3.41 mm. The multiplication time is 4.4 ns at a 3.5-V power supply.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>

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