Low Power Design and Implementation of Multi-Output Carry Look-Ahead Adder

Abstract

Adders are the most elementary and important blocks in Digital Electronics. Adder designs are constrained by time required for carry propagation. Sum generation takes place only after carry propagates from previous bit. This sequential relation increases delay. In this work, Carry Look-Ahead Adder (CLA) is implemented based on Domino logic. Domino logic has the advantages of realizing the circuit using lesser number of transistors compared to CMOS logic. Manchester Carry Chain (MCC) is one of the variants of domino logic to obtain multiple carry outputs simultaneously. This avoids the sequential carry generation dependence. MCC based CLA has capacity to generate 4 carry outputs simultaneously. In the proposed CLA, odd and carry outputs are evaluated using separate carry chains. 8 carry outputs are generated simultaneously. Thus the proposed CLA reduces delay by 47.23% compared to MCC CLA. Power dissipated by proposed CLA is 5.67% more compared to MCC CLA. Proposed CLA has disadvantage of higher power dissipation compared to MCC CLA. Solution for mitigating power in proposed CLA is realized by adding Header Switch based Sleep Transistor (HSST). HSST based proposed CLA consumes 23.02% less power compared to proposed CLA. Delay of the HSST based CLA with odd and even carry chain adder increased by 36.25% with respect to proposed CLA. Power-Delay-Product (PDP) of HSST based proposed CLA is 41.323% higher compared to MCC CLA and Proposed CLA has PDP improvement of 44.055% compared to MCC CLA. HSST based proposed CLA can be used as trade-off between power and delay between MCC CLA and proposed CLA.