A novel germanium implanted salicide technology for CMOS VLSI

Abstract

A novel salicided twin-tub CMOS process using germanium implantation has been developed and characterized. Implantation of n/sup +/ and p/sup +/ dopants after titanium salicidation is used to fabricate devices with low junction leakage and good short-channel effects. The technology is based on a conventional twin-tub CMOS process that uses LTO sidewall spacers for both the LDD (lightly doped drain) and salicide formation. The high-dose phosphorus and boron implants that are performed through the silicide layer to form the n/sup +/ and p/sup +/ regions result in an enhanced diffusivity in the n/sup -/ and p/sup -/ regions, causing anomalously deep source-drain junctions with degraded device punchthrough leakage. This is confirmed by electrical measurements. Since the projected implantation range for phosphorus is greater than arsenic, thicker titanium silicide layers with lower sheet resistance are possible. Spreading resistance and electrical device measurements indicate that the lateral diffusion of the n/sup -/ and p/sup -/ regions is reduced by as much as 0.15 mu m when germanium implantation is performed prior to titanium deposition. Diode leakage was less than 10 nA/cm/sup 2/ for a 5 V bias at room temperature for both cases. >