Abstract
A simple novel fingered stacked capacitor cell with dimensions suitable for 64 Mbit DRAM has been successfully fabricated and electrically tested. The key to the formation of this capacitor cell is the selection of materials with different Wet etch characteristics that can be deposited alternately in the same process chamber. The main advantages of this process are the process simplicity and lower cost of ownership (COO). Results are shown with oxide materials [thermal chemical vapor deposition (CVD) oxide and plasma CVD oxide] having etch selectivities of 4:1 (thermal CVD: plasma CVD) but other materials such as BN or with etch selectivity of up to 2000:1 could be used to improve the controllability of the process. Compared with a straight wall chimney capacitor, this novel fingered cell (using alternating oxide layers) has a 2X increase in capacitance per cell. The 2X capacitance increase was achieved without significant addition in fabrication process complexity, without additional lithography requirements, and without compromising the integrity of the node dielectric due to the formation of the fingers.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
