Abstract
In this paper, a high resolution of 16 bit and high speed of 125MS/s, multibit Pipelined ADC with digital background calibration is presented. In order to achieve low power, SHA-less front end is used with multibit stages. The first and second stages are used here as a 3.5 bit and the stages from third to seventh are of 2.5 bit and last stage is of 3-bit flash ADC. After bit alignment and truncation of total 19 bits, 16 bits are used as final digital output. To precise the remove linear gain error of the residue amplifier and capacitor mismatching error, a digital background calibration technique is used, which is a combination of signal dependent dithering (SDD) and butterfly shuffler. To improve settling time of residue amplifier, a special circuit of voltage separation is used. With the proposed digital background calibration technique, the spurious-free dynamic range (SFDR) has been improved to 97.74 dB @30 MHz and 88.9 dB @150 MHz, and the signal-to-noise and distortion ratio (SNDR) has been improved to 79.77 dB @ 30 MHz, and 73.5 dB @ 150 MHz. The implementation of the Pipelined ADC has been completed with technology parameters of 0.18μm CMOS process with 1.8 V supply. Total power consumption is 300 mW by the proposed ADC.
Highlights
Various digital applications, such as communication base stations, cable head end, professional HDTV cameras and video digitizers require Analog to Digital Converters (ADCs) of high-resolution, high-speed and low cost [1], [2] and [3]
It’s a big challenge for designers to implement a low power Pipelined ADC of high sampling rates with more than 16-bit resolution, which could be good for high speed data communication
As Sample and Hold Amplifier (SHA)-less front-end has been used in this Pipelined ADC, both the multiplying DAC (MDAC) and the flash concurrently are able to sample the input signal
Summary
Various digital applications, such as communication base stations, cable head end, professional HDTV cameras and video digitizers require Analog to Digital Converters (ADCs) of high-resolution, high-speed and low cost [1], [2] and [3]. The dedicated front-end Sample and Hold Amplifier (SHA) has been removed, which permits ADC to use a smaller input sampling capacitor to facilitate its drivability. Reducing the number of those stages which contribute to noise is the best solution to increase SNDR and SFDR without using large sampling capacitors In this way, other stages of Pipelined ADC can work well even with smaller sampling capacitors to minimize the overall circuit’s noise and power. To achieve high SNDR, it requires a large sampling capacitors, which increases power dissipation along with circuit complexity. SHA-less front-end has been chosen to achieve low power, high SNDR, high SFDR and minimum value of sampling capacitors but at the price of circuit complexity for sampling frequencies near 200 MHz
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