A fully digital calibration technique for nonlinearity correction in pipelined ADCs

Abstract

A digital background calibration is proposed to address finite dc gain of amplifier, capacitors mismatch and nonlinearity of amplifier. Two extra comparators and an interpolation filter are utilized to implement a virtual ADC. The proposed calibration, calibrate gain error and nonlinearity of a 1.5 bits per stage pipelined ADC. The difference of virtual ADC and the ADC are utilized to drive a Least Mean Square (LMS) machine to estimate inverse coefficient of Multiplying Digital to Analog Converter (MDAC). The proposed calibration is tested on 12 bit, 100 MS/s pipelined ADC. The capacitor mismatch is set to 0.1% and the amplifier gain is set to 30 dB. The spurious free dynamic range (SFDR) and signal to noise and distortion ratio (SNDR) are both increased from 40 dB and 35.5 dB to 87 dB and 73 dB respectively.