A Digital Background Calibration Technique for Successive Approximation Register Analog-to-Digital Converter

Ling Du,Yang Liu,Ning Ning,Shuangyi Wu,Qi Yu

doi:10.4236/jcc.2013.16006

Abstract

A digital background calibration technique that corrects the capacitor mismatches error is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in SAR ADC which is based on tri-level switching. The termination capacitor in the Digital-to-Analog Converter (DAC) is regarded as a reference capacitor and the digital weights of all other unit capacitors are corrected with respect to the reference capacitor. To make a comparison between the size of the unit capacitor and that of the reference capacitor, each input sample is quantized twice. The unit capacitor being calibrated is swapped with the reference capacitor during the second conversion. The difference between the two conversion results is used to correct the digital weight of the unit capacitor under calibration. The calibration technique with two reference capacitors is presented to reduce the number of parameters to be estimated. Behavior simulation is performed to verify the proposed calibration technique by using a 12-bit SAR ADC with 3% random capacitor mismatch. The simulation results show that the Signal-to-Noise and Distortion Ratio (SNDR) is improved from 57.2 dB to 72.2 dB and the Spurious Free Dynamic Range (SFDR) is improved from 60.0 dB to 85.4 dB.

Highlights

As the dimension of CMOS technology continues to scale down, the advantages of successive approximation register analog-to-digital converter (SAR ADC) become prominent over other ADC architectures due to its simple structure
Calibration of capacitor mismatch error is indispensable for high resolution SAR ADC if small unit capacitors are used
In the proposed calibration technique, the termination capacitor in the Digital-toAnalog Converter (DAC) is regarded as a reference capacitor and the digital weights of all of other unit capacitors are corrected with respect to the reference capacitor

Summary

Introduction

As the dimension of CMOS technology continues to scale down, the advantages of successive approximation register analog-to-digital converter (SAR ADC) become prominent over other ADC architectures due to its simple structure. Digitaldomain background calibration is more preferred than analog-domain calibration as the design complexity is transferred to digital circuits which can benefit from the device scaling of CMOS technology. Two identical SAR ADCs are used to quantize the input signals The difference of their output codes is used to estimate the digital weights of the capacitors. The difference between the two quantization results is used to calculate the actual weight of each capacitor In this calibration algorithm, the input dynamic range is reduced due to the offset injection. This work presents a digital background calibration technique to correct the capacitor mismatch errors in SAR ADC with tri-level switching. In the proposed calibration technique, the termination capacitor in the DAC is regarded as a reference capacitor and the digital weights of all of other unit capacitors are corrected with respect to the reference capacitor.

Tri-Level Switching

Basic Principle

Calibration Technique with Two Reference Capacitors

Simulation Results

Conclusion