A novel design of an efficient Low Power Phase Frequency Detector for Delay Locked Loop

Abstract

The design of Low Power Low Glitch Dynamic Phase Frequency Detector (PFD) is proposed in this paper. The dynamic PFD helps Delay Locked Loop (DLL) to detect the phase error information in form of pulses at high frequency and plays an important role for improving the performance of complete DLL block. A Low Power and Low glitch phase frequency detector is proposed at 180 nm technology node using GPDK180 library with supply voltage VDD=1.8 V in Cadence Virtuoso for schematic composer, Spectre tool for simulations and Cadence Layout editor for layout. By simulating the proposed PFD block, significant reduction in area and power dissipation was observed. Also phase sensitivity has improved significantly and there is no reset path present. It was observed that the proposed dynamic PFD has very low glitch as compared to conventional D flip-flop based PFD. This PFD is designed for low power Delay Locked Loop.