A novel class of decimation filters for ΣΔ A/D converters

Abstract

AbstractA major bottleneck to the design of a truly wideband reconfigurable Software Radio (SR) transceiver is the front end of the system. It is desirable to push the analog‐to‐digital boundary of the SR transceiver as close to the antenna as possible. This places great demands on analog‐to‐digital converters that must produce high‐resolution samples of the incoming signal centered around a carrier frequency in the gigahertz range. A very promising architecture for the design of such converters is the ΣΔ architecture. A critical component of the ΣΔ converter is the rate‐conversion filter that is responsible for rejection of the out‐of‐band noise. Cascaded‐Integrator‐Comb (CIC) filters are efficient antialiasing rate‐conversion filter structures realized by cascading integrator and comb cells separated by a decimation block. High‐order structures, attempting to increase the rejection of the out‐of‐band noise that folds into the useful signal bandwidth because of the decimation, have the drawback of inserting multiple zeroes in the same positions throughout the stop‐band and to increase the edge‐band attenuation.In this paper, we propose a class of decimation filter architectures composed of a cascade of modified CIC filters, which have higher attenuation of the quantization noise produced by a ΣΔ modulator around the folding bands and lower passband drop than classic CIC structures. The design criteria of the proposed filters are described, with the goal of maximizing the denoising effect and minimizing the passband drop, and the problem of the practical realization of the proposed decimation scheme is addressed. Simulations confirm the effectiveness of the proposed decimation filter architectures. Copyright © 2002 John Wiley & Sons, Ltd.