A Novel Capacitorless 1T DRAM Cell for Data Retention Time Improvement

Abstract

This paper proposes a silicon-with-partially-insulating-layer-on-silicon-on-insulator (SISOI) one-transistor dynamic random access memory (1T DRAM) cell to increase data retention time. A conventional 1T DRAM cell has a data retention problem because it stores holes in an SOI layer, which is not separated from the source/drain region. However, the proposed SISOI 1T DRAM cell can keep holes electrically separated from the source/drain region, which leads to the increase of data retention time.